EEPROMs (Electrically Erasable Programmable Read-Only Memories) and flash memories are known as non-volatile semiconductor memory devices capable of electrically writing and erasing data.
Since a memory cell can be constituted by one memory cell in a flash memory having a stacked gate type memory cell structure, the steps of manufacturing the memory can be simplified, the unit price per bit reduced and a high integration density, as well as a large capacity be attained. For these reasons, the flash memory has gained a wide application mainly as a substitute for magnetic recording media such as hard disks and floppy disks.
A selective oxidation process such as a LOCOS (local oxidation of silicon) process is known as a device isolation method conventionally used for semiconductor devices such as non-volatile semiconductor memory devices. The LOCOS process has the advantages that the fabrication method is simple, and the occurrence of defects can be relatively easily controlled because inclination at the boundary between device isolation regions and device regions is not abrupt.
However, as the devices have been miniaturized to meet requirements for higher integration density, the following problems arise. From the standpoint of device processing, there occur the problems of device isolation pitch and the thickness of the device isolation oxide film in connection with the occurrence of bird's beaks. With respect to electrical characteristics, there arise the problems of field inversion, narrow channel effect, and punch-through in connection with diffusion of an impurity in a transverse direction.
A conventional non-volatile semiconductor memory device in which device isolation is effected by using the LOCOS process is explained with reference to FIG. 9. This figure is a sectional view of a conventional stacked gate type EEPROM memory cell in a direction of a word line (control gate) in which device isolation is effected by the LOCOS process.
In FIG. 9, a device isolation oxide film 302 is formed on a silicon substrate 301 by the LOCOS process, and a floating gate 304 comprising a polycrystalline silicon film is formed in a device region between the device isolation oxide films 302 through a tunnel oxide film 303, and a word line (control gate) 306 comprising a polycrystalline silicon film is formed over the floating gate 304 through an insulating film 305.
Because the structure effects device isolation by using the LOCOS process, the problems described above hinder miniaturization and higher integration density. In the case of the EEPROM and the flash memory, in particular, a high voltage of at least 5 V is applied to the word line 306 at the time of write and erase and consequently, a parasitic channel is likely to be formed below the device isolation oxide film 302. Therefore, specific counter-measures must be taken.
A trench device isolation method shown in FIG. 10 has been therefore proposed. FIG. 10 is a sectional view of a stacked gate EEPROM memory cell according to the trench device isolation method in the direction of the word line.
Referring to FIG. 10, a floating gate 405 comprising a polycrystalline silicon layer is shown formed over a silicon substrate 401 through a tunnel oxide film layer 404, and a control gate 407 comprising a polycrystalline silicon layer is formed over the floating gate 405 through an insulating layer 406. The silicon substrate 401, the floating gate 405 and the control gate 407 are isolated for each memory cell by a trench 409. The trench 409 is buried by a boron phosphorus silicate glass (BPSG) film 402 through a trench insulating film 403, and the control gate 407 is connected to the word line 408 made of tungsten silicide.
In this structure, the device regions are isolated by the trenches 409 and at the same time, the floating gate 405 as well as the control gate 407 are isolated for each memory cell. Therefore, this structure provides a very small cell area.
With to the trench isolation method shown in FIG. 10, however, there remains the problem that, because the trenches must be formed in the substrate, the fabrication process is complicated, and that control of defects occurring at the time of forming the trenches is also difficult.